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Question 156Asked in CIL MT Systems, 26 Mar 2017 (12:30 PM)

A flip-flop has a 20-nano second delay from the time its CP input goes from 1 to 0 to the time the output is complimented. What is the maximum delay in a…

A flip-flop has a 20-nano second delay from the time its CP input goes from 1 to 0 to the time the output is complimented. What is the maximum delay in a 16-bit binary ripple counter that uses these flip-flops?
  1. A20 ns
  2. B320 ns
  3. C36 ns
  4. D16 ns
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Correct answer: (B) 320 ns

From CIL MT Systems PYQ, 26 Mar 2017 (12:30 PM)

This is question 156 of CIL MT Systems PYQ, 26 Mar 2017 (12:30 PM). See all questions of this paper with answers, or attempt the paper as a timed online test to get your score and all-India rank.