Question 162Asked in CIL MT Systems, 24 Aug 2026 (3:00 PM, CBT-26)

If a D Flip-Flop has D = 1 and a rising edge of the clock occurs, what will the Q output be with reference to Sequential Circuits?

  1. AToggle
  2. BUndefined
  3. C0
  4. D1
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Correct answer: (D) 1

From CIL MT Systems PYQ, 24 Aug 2026 (3:00 PM, CBT-26)

This is question 162 of CIL MT Systems PYQ, 24 Aug 2026 (3:00 PM, CBT-26). See all questions of this paper with answers, or attempt the paper as a timed online test to get your score and all-India rank.