Computer Organization & Architecture Previous Year Questions

Explanation

Memory capacity is 2ᵐ Kbytes = 2^(m+10) bytes, so the whole memory can be addressed with m + 10 bits. 2ⁿ operations can be represented by n bits. An instruction of the form OP, operand₁, operand₂, operand₃ will therefore take 3(m + 10) + n = 3m + n + 30 bits. So the answer is (d).

Explanation

Ν₀ = 200 failures, μ = 100 failures, λ₀ = 20 failures/CPU hr. Current failure intensity = λ₀(1 − μ/ν₀) = 20(1 − 100/200) = 20(1 − 0.5) = 10 failures/CPU hr. So the answer is (b).

Explanation

A microprocessor is a computer processor which incorporates the functions of a computer's control processing unit (CPU) on a single integrated circuit (IC), or at most a few integrated circuits. A microcomputer is small, relatively, inexpensive computer with a microprocessor as its control processing unit (CPU). It includes a microprocessor, memory, and minimal input/output (I/O) circuitry mounted on a single printed circuit board. That means, microprocessor does not contain input/output devices.

Explanation

Simulating LRU with 4 frames gives 10 page replacements (faults after the frames are filled), and the optimal page replacement algorithm gives 7 replacements. So the correct answer is (b).

Explanation

Total inputs to the ROM = 8 + 8 (two 8-bit numbers) + 1 (mode) + 1 (carry in) = 18, so the ROM has 2¹⁸ words. Outputs = 8 result bits + 1 carry out + 1 overflow = 10 bits. Hence the ROM size is 2¹⁸ × 10.

Explanation

Internal interrupts occur due to internal errors (like division by zero) and external interrupts come from hardware. Software interrupts are the most appropriate way to switch from user mode to supervisor (kernel) mode.

Explanation

Reading of two process won't create any problem, So answer is (c)

Explanation

Data bits: d₈ = 0, d₇ = 0, d₆ = 1, d₅ = 1, d₄ = 1, d₃ = 0, d₂ = 0, d₁ = 1. Stored check bits p₈p₄p₂p₁ = 0111. Codeword layout (positions 12 to 1): d₈ d₇ d₆ d₅ p₈ d₄ d₃ d₂ p₄ d₁ p₂ p₁. Syndrome = 0111 XOR 1101 = 1010 = 10, so bit position 10, which holds d₆, is in error. Flipping d₆ gives the word that was read: 00011001.

Explanation

Since minimum bus cycle duration = 4 clock cycle bus clock = 8 MHZ then, maximum bus cycle rate = 8 m/4sec = 2m/sec Data transferred per bus cycle = 16 bit = 2 B Data transfer rate per second = bus cycle rate × data per bus cycle = 2 M × 2 = 4 × 10⁶ bytes/sec So, option (b) is correct.

Explanation

CPU speed is 1 MIPS = 10⁶ instructions per second. With programmed I/O, each byte transferred needs about one instruction-equivalent of 4 machine cycles (status check, branch, read/write data), so the maximum transfer rate = 10⁶ / 4 = 250,000 bytes/sec = 250 Kbytes/sec.

Explanation

It is the responsibility of loader to transfer executable files from hard disk to main memory. Debugger is a computer program that is used to test and debug other-programs (target program). Compiler is a software which converts a program written in high level language (Source Language) to low level language. Linker takes object files, links them with each other and with any library files that you specify and produces an executable output file.

Explanation

System calls are invoked from user mode by a software interrupt (trap). A privileged instruction cannot be the answer because privileged instructions cannot be executed in user mode.

Explanation

1 character = 1 byte and a 32-bit word = 4 bytes. At 4800 characters per second, one word is assembled every 1/1200 sec, so 1200 words are transferred per second by cycle stealing. The CPU executes 1 million instructions per second, so the slowdown = (1200/1000000) × 100 = 0.12%.

Explanation

Priority of hardware interrupts in 8085: TRAP > RST 7.5 > RST 6.5 > RST 5.5 > INTR. INTR is a level-triggered, maskable interrupt and has the lowest priority.

Explanation

A memory management unit (MMU), sometimes called paged memory management unit (PMMU), is a hardware unit through which all memory references pass, primarily performing the translation of virtual memory addresses to physical addresses.

Explanation

In 1 msec (10⁶ nsec) there are 32 refresh cycles, each taking 100 nsec, so refresh time per msec = 32 × 100 = 3200 nsec. Equivalently, per memory cycle of 250 nsec, refresh cycles = (32 × 250)/10⁶ and refresh time = ((32 × 250)/10⁶) × 100 = 0.8 nsec; percentage = (0.8/250) × 100 = 0.32%.

Explanation

Instruction pipelining is a technique that implements a form of parallelism called instruction level parallelism with a single processor. It therefore allows faster CPU throughput than would otherwise be possible at a given clock rate.

Explanation

(i) A dynamic linker is the part of an operating system that loads and links the shared libraries needed by an executable when it is executed (at “run time”), by copying the context of libraries from present storage to RAM, and filling jump tables and relocating pointers. (ii) Static linker has reduction in overall program execution time than dynamic linker.

Explanation

In write through method, data is written into the cache and the corresponding main memory location at the same time.

Explanation

MVI A, 35H: A = 35H. MOV B, A: B = 35H. STC: carry = 1. CMC: carry = 0. RAR: rotate A right through carry, A = 0001 1010 (1AH). XRA B: (0001 1010) XOR (0011 0101) = 0010 1111 = 2FH.

Explanation

ALU is designed to operate on 8-bit data therefore the 8085 microprocessor has 8-bit ALU.

Explanation

DAD H: double add HL to HL⇒HL=HL+HL

Explanation

The '5' in 8085 indicates that it uses a single +5 V power supply (by using depletion-mode transistors), rather than the +5 V, –5 V and +12 V supplies needed by the 8080. Its clock speed is 3 MHz.

Explanation

Logical address space = number of pages × page size = 2⁶ × 2⁹ = 2¹⁵, so the logical address needs 15 bits. Physical address space = number of frames × page size = 2⁵ × 2⁹ = 2¹⁴, so the physical address needs 14 bits.

Explanation

A synchronous interrupt is one whose source is in phase with the system clock, i.e. interrupts that depend on the system clock (example: a time service that uses the system clock).

Explanation

F1, F2, F3 each with 7 micro-operations need 3 bits each = 9 bits; CD for 4 status bits needs 2 bits; BR with 4 options needs 2 bits; ADF for 128 locations needs 7 bits. Total = 9 + 2 + 2 + 7 = 20 bits.

Explanation

AC is the auxiliary carry flag, CY is the carry flag and Z is the zero flag. All these flags are affected by arithmetic operations.

Explanation

The 8085 microprocessor has a 16-bit address bus, so 2¹⁶ = 65,536 different memory locations can be addressed.

Explanation

Components of a memory tube (direct-view storage tube) display include the flooding gun, primary (writing) gun, collector, storage grid, screen, ground (base) and focusing and deflection system. Liquid crystal is not a component of a memory tube display.