Digital Logic & Number Systems Previous Year Questions

Explanation

A self-dual function is fixed by its values on one half of the input combinations: the 2ⁿ input combinations form 2ⁿ⁻¹ mutually complementary pairs, and the function's value on one member of each pair determines its value on the other. So the number of self-dual functions is 2^(2^(n−1)).

Explanation

In a JK flip-flop, when J = 1 and K = 1, Q toggles between 0 and 1 continuously as long as the clock is enabled, so the final value of Q is uncertain (race condition). The master-slave JK flip-flop is used to resolve this problem.

Explanation

In register indirect addressing the address of the operand is held in a register, so memory can be referenced without having a full memory address in the instruction. Hence the answer is (d).

Explanation

Six 1200 bps terminals give 6 × 1200 = 7200 bps, and n 300 bps terminals give 300n bps. 7200 + 300n = 9600 ⇒ 300n = 2400 ⇒ n = 8. So the answer is (b).

Explanation

The Excess-3 decimal code is a self-complementing code because the binary sum of a code and its 9's complement is equal to 9 and the complement can be generated by inverting each bit pattern.

Explanation

To add two BCD digits we need two 4-bit adders: the first adds the two BCD numbers and the second corrects the result to a valid BCD number. The first 4-bit adder needs 3 full adders and 1 half adder (giving A₃ A₂ A₁ A₀). In the correction step 0110 is added to A₃ A₂ A₁ A₀. A₀ is always added to 0, so no adder is needed; A₁ is added to 1 with no incoming carry, so a half adder is used; A₂ is added to 1 plus a carry, so a full adder is used; A₃ is added only to the carry, so a half adder is used. Total = 3 + 1 = 4 full adders and 1 + 2 = 3 half adders.

Explanation

S₁: Boolean expressions and logic networks correspond to labeled acyclic digraphs. S₂: Minimal expressions do not always give the simplest network. S₃: Greedy K-map grouping may not give an optimal expression. So S₁, S₂ and S₃ are all correct.

Explanation

Given octal No. is (2550276)₈ = (010 101 101 000 010 111 110)₂ ⇒ (01 010 1101 0000 1011 1110)₂ ⇒ (0AD0BE)₁₆ (AD0BE)₁₆

Explanation

Remember with 'n' number of flip-flop you can get upto maximum modulo - (2ⁿ) counter. Since 2⁹ = 512 > 272 it can satisfy the condition.

Explanation

A CPU handles interrupt by executing interrupt service subroutine by checking the interrupt register after finishing the executing of the current instruction.

Explanation

(AB' + AB'C + AC)(A'C' + B') = (AB'(1 + C) + AC)(A'C' + B') = (AB' + AC)(A'C' + B') = AA'B'C' + AB'B' + AA'CC' + AB'C = 0 + AB' + 0 + AB'C = AB'(1 + C) = AB'

Explanation

bit rate = no. of channels × Input bit rate = 4 × 100 kbps = 400 kbps

Explanation

Racing is problem of toggling more than once when the inputs are J = 1 and K = 1. The proper combination of propagation delay and edge triggering prevents the racing problem.

Explanation

The displacement addressing mode is similar to register indirect addressing mode, except that an offset is added to the contents of the register. The offset and register are specified in the instruction. Based Indexed Addressing: The operand’s offset is sum of the content of a base register BX or BP and an index register SI or DI. Based Indexed plus displacement addressing mode: In this mode of addressing the operand’s offset is given by offset=[BX or BP]+[SI or DI]+8 bit or 16 bit displacement. Indexed addressing mode: The operand’s offset is the sum of the content of an index register SI or DI and an 8 bit or 16 bit displacement. So, option (D) is correct.

Explanation

(326.4)₈ = (3 × 8² + 2 × 8¹ + 6 × 8⁰ + 4 × 8⁻¹)₁₀ = (214.5)₁₀. (326.4)₈ = (011 010 110.100)₂ = (1101 0110.1000)₂ = (D6.8)₁₆.

Explanation

In 1's complement there are two representations of zero: –0 (11111111) and +0 (00000000). In 2's complement there is only one representation of 0 (00000000), so 2's complement is the most efficient for performing arithmetic operations on numbers.

Explanation

Grouping the 1s of the K-map: row AB gives AB; the cells with A = 1 and D = 1 give AD; the cells with A = 1 and C = 1 give AC; and cell A'BCD is covered by BCD. Therefore f = AB + AC + AD + BCD.

Explanation

G1 = (x + y)'. G2 = (x + (x + y)')' = x'(x + y) = x'y. G3 = (y + (x + y)')' = y'(x + y) = xy'. f = x'y + xy' = x ⊕ y, i.e. EXCLUSIVE-OR.

Explanation

Half adder adds 2 bits; full adder adds 3 bits; a controlled inverter transmits a binary word or its 1's complement; a binary adder adds two binary numbers. So A-iii, B-i, C-iv, D-ii. Hence, answer is (d).

Explanation

~(~p∧q) ∧ ~(~p∧~q) = (p ∨ ~q) ∧ (p ∨ q) = p ∨ (~q ∧ q) = p. So the function is p ∨ (p ∧ r) = p(1 + r) = p.

Explanation

XOR is linearly inseparable. NOTXOR is just XOR with the 1's swapped with 0's and vice versa; swapping the labels on the points does not alter the structure of the space, so NOTXOR is also linearly inseparable. AND, OR and NOR are linearly separable.

Explanation

A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an external clock. All subsequent flip-flops are clocked by the output of the preceding flip-flop. Asynchronous counters are also called ripple counters because of the way the clock pulse ripples its way through the flip-flops.

Explanation

Interrupt Mask Register (IMR): An Interrupt mask register is a specialized register in a computer's CPU or a dedicated peripheral used to enable or disable (mask) individual interrupt lines.

Explanation

In register indirect addressing, the location (address) of the operand in memory is held in a register that is specified in the instruction.

Explanation

(0.4051)₈ = 0×8⁰ + 4×8⁻¹ + 0×8⁻² + 5×8⁻³ + 1×8⁻⁴ = 0 + 0.5 + 0 + 0.009765625 + 0.000244140625 = (0.510009765625)₁₀ ≈ 0.5100098

Explanation

(2357)₈ = (010 011 101 111)₂. Grouping into 4 bits from right to left: 0100 1110 1111, so it is (4EF)₁₆.

Explanation

Let x = 2³ = 8 = 1000; then x – 1 = 7 = 0111. Now x & (x – 1) = 0000 (& is bitwise AND: a result bit is 1 only if both compared bits are 1, otherwise 0). So for any power of 2 the result is all zeros.

Explanation

For a 3-bit down counter using J-K flip-flops (in toggle mode): J₀ = K₀ = 1, J₁ = K₁ = Q₀' and J₂ = K₂ = Q₁' Q₀'. So II, IV and VI.

Explanation

AX consists of AH and AL. mov al, 15 → AX = 000FH mov ah, 15 → AX = 0F0FH xor al, al → AX = 0F00H mov cl, 3 → AX = 0F00H, CL = 03 shr ax, cl → AX = 01E0H (shift right 3 times) add al, 90H → AX = 0170H, carry = 1 adc ah, 0 → AX = 0270H (adds the carry) So AX = 0270H.

Explanation

(AL) = 3AH = 00111010, (BL) = 49H = 01001001. AL – BL = 11110001, so (AL) = F1H, CF = 1, SF = 1. The carry (borrow) flag is set since the first operand is less than the second; the result is negative, so the sign flag is set.

Explanation

In a microprogrammed control unit, the next address generator (sequencer) supplies the address to the control address register (B), which addresses the control memory (C); the control word read from control memory supplies the next address information. So B is the control address register and C is the control memory.

Explanation

LXI rp, data (load register pair immediate) loads a register pair with 2 bytes of immediate data. It is generally used to load SP or a memory pointer; the pairs used are H-L, D-E and B-C, where B, D, H hold the MSB and C, E, L hold the LSB.

Explanation

Regression testing verifies that previously developed and tested software still performs correctly after it is changed, so I is true. Equivalence partitioning is a black-box (not white-box) testing method, so II is false.

Explanation

Top-down testing proceeds from the main module to sub-modules; a sub-module not yet developed is simulated by a temporary program called a STUB. Bottom-up testing proceeds from sub-modules to the main module, using DRIVERS to simulate the main module. So only I is true.

Explanation

From α ⊃ β and α infer β is Modus Ponens (not Modus Tollens), and Modus Tollens infers ¬α from α ⊃ β and ¬β. R2 is not Modus Ponens either. So neither R1 nor R2 is correct.

Explanation

Group the bits in threes from the right: 001 011 101 011. 001 = 1, 011 = 3, 101 = 5, 011 = 3. So (1011101011)₂ = (1353)₈.

Explanation

Grouping the 1s: columns AB = 01 and 11 give B, the row CD = 11 together with the cell AB = 10, CD = 01 give CD and AD. SOP form = AD + CD + B = (A + C).D + B.

Explanation

In the Boolean product, multiplication is replaced by logical AND and addition by logical OR. Row i of A ⊙ B is the OR of the rows of B selected by the 1s in row i of A: row 1 = B1 = 1110, row 2 = B2 = 0110, row 3 = B1 ∨ B2 = 1110, row 4 = B3 = 1011. So option (a) is correct.

Explanation

After the rotate and shift instructions al = 00011110, and mul cl multiplies it by 2 (append a 0 bit at the LSB): ax = 0000000000111100 = 003CH. For mul, CF = 0 when the high byte of the result is 0 and CF = 1 otherwise; here the high byte is 0, so CF = 0. Hence ax = 003CH; CF = 0.

Explanation

Odd binary numbers end with 1 in the LSB and even numbers end with 0. Only 0*1*0*1+ always ends with at least one 1, so its language contains no even values.

Explanation

Standard planning algorithms assume the environment to be both deterministic and fully observable.