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CIL MT · Computer Science

Computer Organization & Architecture Previous Year Questions

16 Computer Organization & Architecture (Computer Science) questions asked in CIL MT previous year papers, each with the correct answer and explanation. Read them free on UTpaper, or attempt the full papers as timed online tests.

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Other Computer Science topics

Data Structures 56DBMS & SQL 53Theory of Computation & Compilers 27Digital Logic & Number Systems 26Computer Networks 22Operating Systems 21Algorithms 16Programming in C/C++ 11Discrete Mathematics 10
Q1CIL MT Systems, 24 Aug 2026 (3:00 PM, CBT-26)
In a machine instruction, what does the opcode primarily define?
  1. AThe size of the instruction in bits.
  2. BThe type of operation the processor should execute.
  3. CThe memory address where data is stored.
  4. DThe number of registers used in execution.
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Correct answer: (B) The type of operation the processor should execute.

Q2CIL MT Systems, 24 Aug 2026 (3:00 PM, CBT-26)
Which of the following best describes the memory hierarchy in a computer system?
  1. ACache → Main Memory → Registers → Secondary Storage
  2. BRegisters → Cache → Main Memory → Secondary Storage
  3. CSecondary Storage → Main Memory → Cache → Registers
  4. DMain Memory → Registers → Cache → Secondary Storage
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Correct answer: (B) Registers → Cache → Main Memory → Secondary Storage

Q3CIL MT Systems, 24 Aug 2026 (3:00 PM, CBT-26)
What we called to the part of an instruction that specifies the operation to be performed?
  1. AComment
  2. BOperand
  3. CLabel
  4. DOpcode
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Correct answer: (D) Opcode

Q4CIL MT Systems, 24 Aug 2026 (3:00 PM, CBT-26)
Which of the following best describes the interaction between CPU and DMA during block transfer?
  1. ACPU transfers data to cache, DMA transfers it to I/O
  2. BCPU supervises every byte of transfer to ensure correctness
  3. CCPU and DMA alternate each word transfer over the bus
  4. DCPU sends control information once, then DMA handles the transfer independently
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Correct answer: (D) CPU sends control information once, then DMA handles the transfer independently

Q5CIL MT Systems, 26 Mar 2017 (12:30 PM)
Which of the following relationships holds for non-random-access memory, where Tₙ = average time to read or write n bits, Tₐ = average access time, n = number of bits and r = transfer rate in bits per second?
  1. ATₐ = Tₙ + n/r
  2. BTₙ = Tₐ + n/r
  3. CTₐ = Tₙ + r/n
  4. DTₙ = Tₐ + r/n
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Correct answer: (B) Tₙ = Tₐ + n/r

Q6CIL MT Systems, 26 Mar 2017 (12:30 PM)
Interrupt generated due to which of the following operations does not belong to program-related interrupt category?
  1. ADivision by zero
  2. BAttempt to execute an illegal machine instruction
  3. CMemory parity error
  4. DReference outside a user's allowed memory space
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Correct answer: (C) Memory parity error

Q7CIL MT Systems, 26 Mar 2017 (12:30 PM)
Consider a cache memory organization with m lines in which the cache is divided into v sets, each of which consists of k lines. The set associative mapping technique reduces to direct mapping when:
  1. Av = m and k = m
  2. Bv = 1 and k = m
  3. Cv = m and k = 1
  4. Dv = 1 and k = 1
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Correct answer: (C) v = m and k = 1

Q8CIL MT Systems, 26 Mar 2017 (12:30 PM)
Consider a memory unit of size 96 K × 16, where the first component represents the total number of words and the second component represents the number of bits per word. What will be the number of address lines and input-output data lines?
  1. A16 address lines, 7 data lines
  2. B7 address lines, 16 data lines
  3. C17 address lines, 16 data lines
  4. D16 address lines, 17 data lines
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Correct answer: (C) 17 address lines, 16 data lines

Q9CIL MT Systems, 27 Feb 2020 (8:00 AM)
The main memory of a computer has 2cm blocks while the cache has 2c blocks. If cache uses set associative mapping scheme with two blocks per set, then the block k of the main memory maps to set:
  1. A(k mod m) of the cache
  2. B(k mod c) of the cache
  3. C(k mod 2c) of the cache
  4. D(k mod 2cm) of the cache
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Correct answer: (B) (k mod c) of the cache

Q10CIL MT Systems, 27 Feb 2020 (8:00 AM)
Consider the following statements: Arithmetic Logic Unit (ALU) 1. Performs arithmetic operations 2. Performs comparisons. 3. Communicates with I/O devices 4. Keeps watch on the system Which of these statements are correct?
  1. A1 Only
  2. B1 and 2 only
  3. C1 and 4
  4. D2 and 3
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Correct answer: (B) 1 and 2 only

Q11CIL MT Systems, 27 Feb 2020 (8:00 AM)
Which of the following affects the processing power of CPU I. Data bus width II. Clock speed III. Address Bus width
  1. AI and III
  2. BI, II and III
  3. COnly I
  4. DOnly II
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Correct answer: (B) I, II and III

Q12CIL MT Systems, 27 Feb 2020 (8:00 AM)
Principle of locality is used in _______.
  1. ARegisters
  2. BDMA
  3. CCache Memory
  4. DInterrupt
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Correct answer: (C) Cache Memory

Q13CIL MT Systems, 27 Feb 2020 (8:00 AM)
What is number of page faults by least recently used page replacement for a memory with 4 frames for the page reference string 2, 0, 1, 2, 4, 0, 5, 1, 4, 6, 4, 2, 1, 3, 0?
  1. A9
  2. B7
  3. C8
  4. D10
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Correct answer: (D) 10

Q14CIL MT Systems, 27 Feb 2020 (8:00 AM)
A computer uses RAM chips of 1024 x 1 capacity. How many chips are needed to provide memory capacity of 16K bytes?
  1. A8
  2. B1024
  3. C16
  4. D128
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Correct answer: (D) 128

Q15CIL MT Systems, 27 Feb 2020 (8:00 AM)
Which of the following has lowest access time?
  1. AMain Memory
  2. BOptical disk
  3. CCache
  4. DRegisters
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Correct answer: (D) Registers

Q16CIL MT Systems, 27 Feb 2020 (8:00 AM)
During DMA transfer, DMA controller transfers data ______.
  1. Adirectly from CPU to Memory
  2. Bdirectly from memory to CPU
  3. Cdirectly between memory and registers
  4. Ddirectly between the I/O module and main memory
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Correct answer: (D) directly between the I/O module and main memory

How to use these CIL MT Computer Science questions

Every question here was asked in a real CIL MT paper; the paper and shift are shown on the card, and the number opens the question on its own page. Try each one before tapping Show answer, then attempt the full CIL MT papers as timed tests to check your speed under exam conditions.

More CIL MT subjects

English 75General Awareness 75Mathematics 75Reasoning 64