Digital Logic & Number Systems Previous Year Questions (page 4)

Explanation

A NAND gate outputs 0 only when all inputs are 1, so if any input is 0 (low) the output is 1 (high). An AND gate would give 0 in that case.

Explanation

An AND gate gives 1 only when both inputs are 1, so y = a·b. The options with complemented inputs describe other functions.

Explanation

(A5)₁₆ = 10 × 16 + 5 = 160 + 5 = 165.

Explanation

The CPU contains registers, the control unit and the ALU. RAM is main memory, which sits outside the CPU and is reached over the bus.

Explanation

325 / 8 = 40 remainder 5, 40 / 8 = 5 remainder 0, 5 / 8 = 0 remainder 5. Reading remainders bottom up gives 505 in octal (5 x 64 + 0 + 5 = 325).

Explanation

11011 = 16 + 8 + 0 + 2 + 1 = 27.

Explanation

In direct (absolute) addressing, the instruction's address field holds the actual memory address of the operand. Immediate addressing holds the data itself and indirect holds the address of the address.

Explanation

NAND and NOR are universal gates precisely because AND, OR and NOT (and hence every other gate) can be built from them alone, so the statement that basic gates cannot be built from them is false.

Explanation

Invert 1100 to get 0011, then add 1: 0011 + 1 = 0100.

Explanation

In a K-map, rows and columns are labelled in Gray code (00, 01, 11, 10) so adjacent cells differ by one bit; plain binary order (00, 01, 10, 11) would break adjacency. K-maps simplify both SOP and POS forms.

Explanation

XOR gives 1 only when its inputs differ (0,1 or 1,0) and 0 when they are the same. AND needs both 1, OR needs at least one 1.

Explanation

Flash memory is non-volatile (NVRAM-type) memory that keeps its data without power, as in pen drives and SSDs. Cache, registers and main RAM are volatile.

Explanation

NAND is NOT-AND, so its output is (xy)'. (x+y)' is NOR, x+y is OR and xy is AND.

Explanation

A DRAM cell stores each bit as charge on a tiny capacitor (with one transistor), which must be refreshed regularly. SRAM uses flip-flops.

Explanation

10 = 1010₂, and 0.25 × 2 = 0.5 → 0, 0.5 × 2 = 1.0 → 1, so 0.25 = .01₂. Hence 10.25 = 1010.01₂.

Explanation

111111₂ = 32 + 16 + 8 + 4 + 2 + 1 = 63 (that is, 2⁶ − 1).

Explanation

When a mobile station enters a new area, the serving VLR registers it and informs the HLR of the location change, so the HLR always knows which VLR area the subscriber is in.

Explanation

Cascading counters multiplies their moduli: 6 × 8 = 48, giving a Mod-48 counter.

Explanation

A sum of 5 occurs 4 ways and a sum of 9 occurs 4 ways out of 36, so P(5 or 9) = 8/36 = 2/9. The required probability is 1 − 2/9 = 7/9.

Explanation

In ADD R1, [R2] the operand's address is held in register R2, which is register indirect addressing.

Explanation

The ripple counter fails when the total delay of 10 flip-flops reaches the clock period: 10 × t_pd = 1/10 MHz = 100 ns, so t_pd = 10 ns.

Explanation

Minterms 0, 2, 4, 6 (all with z = 0) group into z'. Minterms 4 and 5 (x = 1, y = 0) group into xy'. So F = z' + xy'.

Explanation

The ALU contains the circuits for arithmetic (such as binary addition), logic and shift operations. The control unit only directs operations.

Explanation

In register indirect mode the chosen register holds the memory address of the operand, not the operand itself.

Explanation

An assembler translates assembly mnemonics into machine code, and because assembly instructions map to a specific processor's instruction set, the program is machine dependent. Both are true.

Explanation

One-address instructions use an implied accumulator (AC) for all data manipulation, e.g. ADD X means AC = AC + M[X].

Explanation

The Instruction Register (IR) holds the instruction currently being decoded and executed, for use by the control unit.

Explanation

A point-to-point connection gives a dedicated link between exactly two devices. A shared, timeshared link describes a multipoint connection, so only I is correct.

Explanation

The E-Waste (Management) Rules 2016 cover IT and telecom equipment and consumer electrical and electronics, and also include compact fluorescent lamps (CFL) and other mercury-containing lamps. So both apply.

Explanation

UTF-8 is the most widely used Unicode encoding; it uses 1 to 4 bytes per character and is ASCII-compatible. UTF-17, 61 and 35 do not exist.

Explanation

The gate shown has an extra curved line at the input side of the OR shape, which is the symbol for the Exclusive-OR (XOR) gate.

Explanation

Numbers with a decimal point (like 3.14) are fractional/floating point numbers, stored as float in Python. Integers have no decimal part.

Explanation

ASCII uses 7 bits (128 characters), enough mainly for English, so it can handle only one, or at most two, languages.

Explanation

AND outputs 1 only when both inputs are 1, and it is written with the multiplication symbol (A·B). Both are correct.

Explanation

Unicode can be encoded with 8-bit code units, as in UTF-8 (UTF-16 and UTF-32 also exist). 17, 65 and 9-bit formats are not standards.

Explanation

An encoder's output depends only on its present inputs, so it is a combinational circuit. Counters and shift registers have memory, which makes them sequential.

Explanation

Two 4-bit inputs give 2⁸ = 256 combinations. Only 10 × 10 = 100 are valid BCD digit pairs (0-9 each), so 256 − 100 = 156 combinations are invalid.

Explanation

Dividing by 2 is done by shifting the register one bit to the right: 10100 becomes 01010 (20 ÷ 2 = 10).

Explanation

The accumulator's size equals the processor's word length. For a 32-bit processor it is 32 bits = 4 bytes.