DSSSB TGT / PGT · Computer Science

Computer Organization & Architecture Previous Year Questions

63 Computer Organization & Architecture (Computer Science) questions asked in DSSSB TGT / PGT previous year papers, each with the correct answer and explanation. Read them free on UTpaper, or attempt the full papers as timed online tests.

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Q1From DSSSB TGT Computer Science Practice Set 5
A transient of 100 ms is to be captured on a digital storage oscilloscope on full screen in the horizontal direction. If the transient is to be recorded at a sampling rate of 100 KS/s, what should the minimum size of the acqisition memory be ?
  1. A5K
  2. B10K
  3. C15K
  4. D20K
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Correct answer: (B) 10K

Explanation

Samples needed = sampling rate × time = 100,000 per second × 0.1 s = 10,000 samples, so the acquisition memory must hold at least 10K.

Q2From DSSSB TGT Computer Science Practice Set 5
______ is the first Intel x86 microprocessor with a dual core, referring to the implementation of two processors on a single chip.
  1. ACore
  2. BCore 2 duo
  3. CDual core
  4. DCentrino
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Correct answer: (A) Core

Explanation

Following Stallings' list of Intel processors, the Intel Core was the first x86 microprocessor with a dual core, meaning two processors on a single chip. Core 2 Duo came later.

Q3From DSSSB TGT Computer Science Practice Set 5
A computer has 32 MB memory. How many bits are needed to access any single byte in the memory?
  1. A25
  2. B16
  3. C24
  4. D20
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Correct answer: (A) 25

Explanation

32 MB = 32 × 2²⁰ bytes = 2⁵ × 2²⁰ = 2²⁵ bytes, so 25 address bits are needed.

Q4From DSSSB TGT Computer Science Practice Set 5
A computer has 128MB memory. Each word in this computer is of 8 bytes. How many bits are required to address any single word in the memory?
  1. A27
  2. B24
  3. C23
  4. D25
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Correct answer: (B) 24

Explanation

128 MB = 2²⁷ bytes. With 8 bytes (2³) per word that is 2²⁷/2³ = 2²⁴ words, so 24 bits are needed.

Q5From DSSSB TGT Computer Science Practice Set 5
DMA steals cycle from the ______.
  1. AI/O device or Hard disk
  2. BPhysical Memory
  3. CCache Memory
  4. DCentral Processing Unit
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Correct answer: (D) Central Processing Unit

Explanation

In cycle stealing, the DMA controller takes the system bus from the CPU for a memory cycle at a time, so it steals cycles from the CPU.

Q6From DSSSB TGT Computer Science Practice Set 4
Hardware mechanism that enables a device to notify the CPU is called:
  1. ABusy-waiting
  2. BInterrupt
  3. CPolling
  4. DDMA
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Correct answer: (B) Interrupt

Explanation

An interrupt is a hardware signal that a device sends to the CPU to request attention. Polling and busy-waiting are software checks made by the CPU.

Q7From DSSSB TGT Computer Science Practice Set 4
The memory which does not loose its content on failure of power supply is known as ______ memory.
  1. AMain memory
  2. BVolatile
  3. CNon-volatile
  4. DRAM
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Correct answer: (C) Non-volatile

Explanation

Non-volatile memory, such as ROM or flash, keeps its contents when power is lost. RAM (main memory) is volatile.

Q8From DSSSB TGT Computer Science Practice Set 3
______ refers to the amount of time required to position the read – write head of a hard disk on appropriate sector.
  1. ALoad time
  2. BSeek time
  3. CAccess time
  4. DRotational latency
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Correct answer: (B) Seek time

Explanation

Seek time is the time to move the read/write head to the correct track. Rotational latency is the wait for the sector to rotate under the head, and access time is the two combined.

Q9From DSSSB TGT Computer Science Practice Set 3
Which of the following memory is non-volatile?
  1. AROM
  2. BCache
  3. CROM and Cache
  4. DRAM
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Correct answer: (A) ROM

Explanation

ROM keeps its contents when power is off, so it is non-volatile. RAM and cache lose their data when power is removed.

Q10From DSSSB TGT Computer Science Practice Set 3
The following data refer to a hard disk: number of tracks per side = 600; number of sides = 2 ; number of bytes per sector = 512; storage capacity in bytes = 21 504 000. Determine the number of sectors per track for this hard disk.
  1. A35
  2. B40
  3. C45
  4. D50
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Correct answer: (A) 35

Explanation

Capacity = tracks per side × sides × sectors per track × bytes per sector. So sectors per track = 21,504,000 ÷ (600 × 2 × 512) = 21,504,000 ÷ 614,400 = 35.

Q11From DSSSB TGT Computer Science Practice Set 2
Interrupts are sent by ______ and received by ______.
  1. ACPU, I/O Devices
  2. BI/O Devices, CPU
  3. CTimer, I/O Devices
  4. DCPU, ALU
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Correct answer: (B) I/O Devices, CPU

Explanation

Corrected: the book's key says (a). Interrupts are sent by I/O devices and received by the CPU.

Q12From DSSSB TGT Computer Science Practice Set 2
Which of the following is not a program control instruction ?
  1. ACMP
  2. BMOV
  3. CJMP
  4. DCALL
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Correct answer: (B) MOV

Explanation

MOV is a data transfer instruction. JMP and CALL change the flow of control, and CMP is used with jumps to make decisions, so these are program control instructions.

Q13From DSSSB TGT Computer Science Practice Set 1
On which of the following storage media, storage of information is organized as a single continuous spiral groove ?
  1. ACD-ROM
  2. BRAM
  3. CHard disk
  4. DFloppy disk
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Correct answer: (A) CD-ROM

Explanation

A CD-ROM stores data as pits along one continuous spiral track running from the centre outward, while hard disks and floppy disks use concentric circular tracks.

Q14From DSSSB TGT Computer Science Practice Set 1
The technology that stores only the essential instructions on a microprocessors chip and thus enhances its speed is referred to as :
  1. AMIMD
  2. BCISC
  3. CRISC
  4. DSIMD
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Correct answer: (C) RISC

Explanation

RISC (Reduced Instruction Set Computer) keeps only a small set of simple, essential instructions that run in about one clock cycle each, which increases speed. CISC uses many complex instructions.

Q15From DSSSB TGT Computer Science Practice Set 1
In a computer system, memory mapped access takes 100 nanoseconds when a page is found in TLB. In case the page is not TLB, it takes 400 nanoseconds to access. Assuming a hit ratio of 80%, the effective access time is:
  1. A120 nanoseconds
  2. B160 nanoseconds
  3. C200 nanoseconds
  4. D500 nanoseconds
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Correct answer: (B) 160 nanoseconds

Explanation

EAT = 0.8 × 100 + 0.2 × 400 = 80 + 80 = 160 ns.

Q16From DSSSB TGT Computer Science Practice Set 1
Von Neumann computer architecture is ______.
  1. ASISD
  2. BSIMD
  3. CMIMD
  4. DMISD
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Correct answer: (A) SISD

Explanation

A Von Neumann machine runs one instruction stream on one data stream at a time, which in Flynn's classification is SISD.

Q17From DSSSB TGT Computer Science Practice Set 1
Which of the following is/are wrong? (A) RAM and ROM are volatile memories, (B) ROMs, PROMs and EPROMs are non-volatile memories. (C) RAM and Dynamic RAM are same. (D) A Random Access Memory (RAM) is a read write memory.
  1. A(A) and (B)
  2. B(A) and (C)
  3. C(A) and (D)
  4. D(C) and (D)
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Correct answer: (B) (A) and (C)

Explanation

(A) is wrong because ROM is non-volatile. (C) is wrong because RAM includes both static and dynamic RAM. (B) and (D) are true.

Q18From DSSSB TGT Computer Science Practice Set 1
Ram and sita's father brought toys for them. Individually (by default) he gifted the boy an airplane. Which feature of social culture is highlighted in the statement?
  1. AMarginalization
  2. BEquality
  3. CFeminism
  4. DStereotype
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Correct answer: (D) Stereotype

Explanation

Automatically giving the boy an airplane, a toy assumed to be "for boys", reflects a gender stereotype.

Q19DSSSB PGT Computer Science (Technical), 11 Jul 2021
Following memory units in descending order. Gigabyte, Megabyte, Exabyte, Zettabyte, Petabyte, Yottabyte
  1. AYottabyte, Zettabyte, Exabyte, Petabyte, Gigabyte, Megabyte
  2. BZettabyte, Yottabyte, Petabyte, Exabyte, Megabyte, Gigabyte
  3. CYottabyte, Exabyte, Petabyte, Zettabyte, Gigabyte, Megabyte
  4. DZettabyte, Petabyte, Yottabyte, Exabyte, Gigabyte, Megabyte
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Correct answer: (A) Yottabyte, Zettabyte, Exabyte, Petabyte, Gigabyte, Megabyte

Explanation

In powers of 1024: yottabyte (2⁸⁰) > zettabyte (2⁷⁰) > exabyte (2⁶⁰) > petabyte (2⁵⁰) > gigabyte (2³⁰) > megabyte (2²⁰).

Q20DSSSB PGT Computer Science (Technical), 11 Jul 2021
How many 16 K x 1 bit RAM chips are needed to provide a memory capacity of 128 K x 1 byte?
  1. A8
  2. B12
  3. C64
  4. D128
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Correct answer: (C) 64

Explanation

Required capacity is 128K × 8 bits. Each chip is 16K × 1 bit, so (128K/16K) × (8/1) = 8 × 8 = 64 chips.

Q21DSSSB PGT Computer Science (Technical), 11 Jul 2021
Which component of computer act as nervous system?
  1. AArithmetic Logic Unit
  2. BInput unit
  3. CControl unit
  4. DStorage unit
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Correct answer: (C) Control unit

Explanation

The control unit directs and coordinates every other part of the computer by sending control signals, just as the nervous system coordinates the body.

Q22DSSSB PGT Computer Science (Technical), 11 Jul 2021
Match the following. I. Batch Processing system — A. Meeting time constraint II. Multi Programming — B. Good response time III. Time sharing — C. Resource utilization IV. Real time — D. CPU idle time
  1. Ai-D, ii-C, iii-B, iv-A
  2. Bi-A, ii-B, iii-C, iv-D
  3. Ci-D, ii-A, iii-B, iv-C
  4. Di-B, ii-C, iii-D, iv-A
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Correct answer: (C) i-D, ii-A, iii-B, iv-C

Explanation

Note: the answer key gives (C), but the logical match is (A): batch processing leaves the CPU idle during I/O, multiprogramming improves resource utilization, time sharing gives good response time, and real-time systems must meet time constraints.

Q23DSSSB PGT Computer Science (Technical), 11 Jul 2021
A free list contains three memory areas of sizes 6 KB, 15 KB and 12 KB. The next three memory requests are for 10 KB, 2 KB and 14 KB. Which of the memory allocation strategy that would be able to accommodate all the three requests?
  1. AWorst Fit
  2. BBest Fit
  3. CNext Fit
  4. DFirst Fit
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Correct answer: (B) Best Fit

Explanation

Best fit: 10 KB→12 KB (2 KB left), 2 KB→the 2 KB hole, 14 KB→15 KB, so all three fit. First, next and worst fit put 10 KB into the 15 KB block, leaving no block for 14 KB.

Q24DSSSB PGT Computer Science (Technical), 11 Jul 2021
Memory buffer which stores the image definition is known as ________.
  1. APixel Buffer
  2. BFrame Buffer
  3. CGraphic Buffer
  4. DPicture Buffer
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Correct answer: (B) Frame Buffer

Explanation

The frame buffer (refresh buffer) is the memory that stores the intensity/colour value of every pixel of the screen image.

Q25DSSSB PGT Computer Science (Technical), 11 Jul 2021
What is the full form of MISD?
  1. AMultiple Interrupt stream and single Data stream
  2. BMultiple Instruction stream and single Data stream
  3. CMany Interrupt stream and single digital stream
  4. DMany Instruction stream and Single Digital stream
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Correct answer: (B) Multiple Instruction stream and single Data stream

Explanation

In Flynn's taxonomy, MISD means Multiple Instruction stream, Single Data stream.

Q26DSSSB PGT Computer Science (Technical), 11 Jul 2021
________ and ________ are planned and organized for improving the power of thinking.
  1. ACurriculum; instructions
  2. BCharts; teaching
  3. CTeaching; instruction
  4. DEvaluation; instructions
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Correct answer: (C) Teaching; instruction

Explanation

Teaching and instruction are planned and organised activities meant to develop learners' thinking power.

Q27DSSSB TGT Computer Science (Technical), 8 Aug 2021, Shift 2
How many address lines and input-output data are needed for the 64k ×8 memory unit?
  1. A16 address line, 3 data line
  2. B6 address line, 3 data line
  3. C16 address line, 8 data line
  4. D10 address line, 8 data line
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Correct answer: (C) 16 address line, 8 data line

Explanation

64K = 2¹⁶ words, so 16 address lines are needed. Each word is 8 bits wide, so 8 data lines are needed.

Q28DSSSB TGT Computer Science (Technical), 8 Aug 2021, Shift 2
How many memory references are to fetch an operand in indirect addressing?
  1. A1
  2. B2
  3. C3
  4. D4
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Correct answer: (B) 2

Explanation

In indirect addressing, the first memory access reads the operand's effective address and the second fetches the operand itself. That is 2 memory references.

Q29DSSSB TGT Computer Science (Technical), 8 Aug 2021, Shift 2
This instruction is of what type? ADD R1, A, B
  1. AZero address Instruction
  2. BTwo address Instruction
  3. COne address Instruction
  4. DThree address Instruction
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Correct answer: (D) Three address Instruction

Explanation

ADD R1, A, B names three operands, a destination R1 and two sources A and B (R1 ← A + B), so it is a three-address instruction.

Q30DSSSB TGT Computer Science (Technical), 7 Aug 2021, Shift 3
How many address lines and input-output data lines are needed in 2k × 16 memory unit?
  1. A10 address line, 16 data line
  2. B10 address line, 4 data line
  3. C11 address line, 4 data line
  4. D11 address line, 16 data line
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Correct answer: (D) 11 address line, 16 data line

Explanation

2K = 2048 = 2¹¹ words, so 11 address lines are needed, and each word is 16 bits, so 16 data lines.

Q31DSSSB TGT Computer Science (Technical), 7 Aug 2021, Shift 3
Pseudo instruction is given to ________.
  1. ACompiler
  2. BLinker
  3. CAssembler
  4. DLoader
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Correct answer: (C) Assembler

Explanation

Pseudo-instructions (assembler directives such as ORG, END, DEC) are commands to the assembler. They are not translated into machine instructions.

Q32DSSSB TGT Computer Science (Technical), 7 Aug 2021, Shift 2
A 500 kbyte memory is managed using variable memory partitions and are allowed for compaction. It is currently 2 partitions of sizes 100 kbytes and 130 kbytes respectively. The smallest allocation request in Kbytes that could be denied is for ________.
  1. A250
  2. B270
  3. C271
  4. D170
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Correct answer: (C) 271

Explanation

Free memory = 500 − (100 + 130) = 270 KB. With compaction, all of it can be joined into one block, so any request up to 270 KB succeeds and the smallest request that can be denied is 271 KB.

Q33DSSSB TGT Computer Science (Technical), 7 Aug 2021, Shift 2
________ is CPU independent machine language style instruction set into which .NET Framework program are compiled.
  1. AMachine Language
  2. BHigh Level Language
  3. CIntermediate Language
  4. DAssembly Language
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Correct answer: (C) Intermediate Language

Explanation

.NET programs are compiled to Intermediate Language (MSIL/CIL), a CPU-independent instruction set that the JIT compiler later turns into native code.

Q34DSSSB TGT Computer Science (Technical), 1 Aug 2021, Shift 3
When there is a memory wastage within the memory partition itself then it is known as ________.
  1. AExternal fragmentation
  2. BInternal fragmentation
  3. CBelady's Anomaly
  4. DCompaction
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Correct answer: (B) Internal fragmentation

Explanation

Internal fragmentation is wasted space inside an allocated partition, when the partition is larger than the process placed in it.

Q35DSSSB TGT Computer Science (Technical), 1 Aug 2021, Shift 1
Disabling an interrupt is known as ________.
  1. AMasking
  2. BRun
  3. CStop
  4. DHalt
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Correct answer: (A) Masking

Explanation

Disabling (masking) an interrupt means setting a mask bit so the CPU ignores that interrupt until it is unmasked.

Q36DSSSB TGT Computer Science (Technical), 13 Sep 2025, Shift 3 (5:00 PM)
Which of the following systems typically DO NOT use contiguous allocation?
  1. ACD-ROM systems
  2. BVideo streaming systems
  3. CGeneral-purpose operating systems with dynamic file sizes
  4. DReal-time systems
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Correct answer: (C) General-purpose operating systems with dynamic file sizes

Explanation

General-purpose OSs have files that grow and shrink, which causes external fragmentation with contiguous allocation. So they use linked or indexed allocation instead.

Q37DSSSB TGT Computer Science (Technical), 13 Sep 2025, Shift 3 (5:00 PM)
If the compiler of the programming language occupies 2-byte memory space for an unsigned integer, then what is the range of the unsigned integer?
  1. A−32768 to 32767
  2. B0 to 65535
  3. C0 to 65536
  4. D0 to 32767
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Correct answer: (B) 0 to 65535

Explanation

2 bytes = 16 bits. An unsigned integer has no sign bit, so it holds 0 to 2¹⁶ − 1 = 0 to 65535.

Q38DSSSB TGT Computer Science (Technical), 13 Sep 2025, Shift 3 (5:00 PM)
Which of the following address lines are typically used for decoding in a system with 16 KB of memory?
  1. AA0–A13
  2. BA0–A10
  3. CA0–A3
  4. DA0–A7
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Correct answer: (A) A0–A13

Explanation

16 KB = 2¹⁴ bytes, so 14 address lines, A0 to A13, are needed to select every location.

Q39DSSSB TGT Computer Science (Technical), 13 Sep 2025, Shift 3 (5:00 PM)
Which of the following is an example of an 8-bit microprocessor?
  1. AIntel 80386
  2. BIntel 8085
  3. CMotorola 68000
  4. DIntel 8086
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Correct answer: (B) Intel 8085

Explanation

The Intel 8085 is an 8-bit microprocessor. The 8086 and 68000 are 16-bit processors, and the 80386 is 32-bit.

Q40DSSSB TGT Computer Science (Technical), 13 Sep 2025, Shift 3 (5:00 PM)
Which of the following is typically stored in control memory?
  1. AData for arithmetic operations
  2. BSystem-level instructions
  3. CMicroprograms and microinstructions
  4. DUser programs
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Correct answer: (C) Microprograms and microinstructions

Explanation

In a microprogrammed control unit, control memory stores the microprograms (sequences of microinstructions) that create the control signals.

Q41DSSSB TGT Computer Science (Technical), 13 Sep 2025, Shift 3 (5:00 PM)
Which part of the CPU is responsible for performing calculations and logical operations?
  1. AMemory Unit
  2. BControl Unit (CU)
  3. CArithmetic Logic Unit (ALU)
  4. DInput Device
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Correct answer: (C) Arithmetic Logic Unit (ALU)

Explanation

The ALU (Arithmetic Logic Unit) performs arithmetic such as addition and subtraction, and logical operations such as AND, OR and comparisons.

Q42DSSSB TGT Computer Science (Technical), 12 Sep 2025, Shift 3 (5:00 PM)
Which of the following is a type of ROM that allows data to be written and erased electrically?
  1. AEPROM
  2. BEEPROM
  3. CMask ROM
  4. DFlash Memory
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Correct answer: (B) EEPROM

Explanation

EEPROM (Electrically Erasable Programmable ROM) can be written and erased with electrical signals. EPROM needs UV light to erase, and mask ROM is fixed at manufacture.

Q43DSSSB TGT Computer Science (Technical), 12 Sep 2025, Shift 3 (5:00 PM)
Which of the following is used to store the data and instructions during execution of the instructions?
  1. AHard Disk Drive
  2. BMemory Unit
  3. CControl Unit
  4. DArithmetic and Logic Unit
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Correct answer: (B) Memory Unit

Explanation

The memory unit (main memory) holds the program instructions and data while they are being executed. The CPU fetches them from there.

Q44DSSSB TGT Computer Science (Technical), 12 Sep 2025, Shift 2 (1:00 PM)
Which of the following statements regarding the Best Fit memory allocation strategy is true?
  1. ABest Fit may cause excessive fragmentation by creating many small unusable holes.
  2. BBest Fit always allocates memory faster since it searches the larger free partition.
  3. CBest Fit prefers allocating memory at the start of the memory block list.
  4. DBest Fit merges adjacent free partitions soon after allocation.
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Correct answer: (A) Best Fit may cause excessive fragmentation by creating many small unusable holes.

Explanation

Best Fit chooses the smallest hole that fits, so the leftover pieces are tiny and often too small to use, causing external fragmentation. It also searches the entire list, so it is not faster.

Q45DSSSB TGT Computer Science (Technical), 12 Sep 2025, Shift 2 (1:00 PM)
In designing a microprogrammed control unit, what is stored in the control memory?
  1. AAddressing modes for memory access
  2. BMicroinstructions that define control signals
  3. CMachine-level instructions
  4. DData values used by the CPU
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Correct answer: (B) Microinstructions that define control signals

Explanation

In a microprogrammed control unit, the control memory (usually ROM) holds the microprograms, i.e. sequences of microinstructions whose bits generate the control signals.

Q46DSSSB TGT Computer Science (Technical), 12 Sep 2025, Shift 2 (1:00 PM)
Which of the following operations is NOT performed by the ALU?
  1. ABitwise operations
  2. BMemory addressing
  3. CArithmetic operations
  4. DLogical comparisons
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Correct answer: (B) Memory addressing

Explanation

The ALU performs arithmetic, logical, bitwise and comparison operations. Memory addressing is handled by the control unit and address registers/MMU, not the ALU.

Q47DSSSB TGT Computer Science (Technical), 12 Sep 2025, Shift 2 (1:00 PM)
In assembly, how is a macro invoked after its definition?
  1. ABy using the JMP instruction
  2. BBy using the CALL instruction
  3. CBy writing its name followed by MACRO
  4. DBy simply writing its name with any required parameters
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Correct answer: (D) By simply writing its name with any required parameters

Explanation

After defining a macro, you invoke it by writing its name (with any arguments) as if it were an instruction; the assembler then expands the macro body in place. CALL is for procedures, not macros.

Q48DSSSB TGT Computer Science (Technical), 12 Sep 2025, Shift 2 (1:00 PM)
Which component is considered the 'brain' of the computer?
  1. AHDD
  2. BRAM
  3. CROM
  4. DCPU
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Correct answer: (D) CPU

Explanation

The CPU processes all instructions and controls the other components, so it is called the brain of the computer. RAM, ROM and HDD are memory and storage.

Q49DSSSB TGT Computer Science (Technical), 12 Sep 2025, Shift 2 (1:00 PM)
How can curriculum content be gender-equitable for girls who are marginalised?
  1. ABy only using native tongues when instructing
  2. BBy only imparting advanced scientific knowledge
  3. CBy pressuring girls to conform to gender norms
  4. DBy providing literacy instruction that boosts self-esteem and changes people's lives
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Correct answer: (D) By providing literacy instruction that boosts self-esteem and changes people's lives

Explanation

A gender-equitable curriculum for marginalised girls gives literacy and life-skill education that builds self-esteem and empowers them to change their lives, rather than reinforcing gender norms.

Q50DSSSB TGT Computer Science (Technical), 12 Sep 2025, Shift 1 (9:00 AM)
Which cycle is primarily managed by the Control Unit?
  1. AI/O cycle
  2. BMemory refresh cycle
  3. CInstruction cycle (Fetch-Decode-Execute cycle)
  4. DArithmetic cycle
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Correct answer: (C) Instruction cycle (Fetch-Decode-Execute cycle)

Explanation

The control unit directs the instruction cycle: it fetches each instruction, decodes it and generates the control signals that carry out its execution.

How to use these DSSSB TGT / PGT Computer Science questions

Every question here was asked in a real DSSSB TGT / PGT paper; the paper and shift are shown on the card, and the number opens the question on its own page. Try each one before tapping Show answer, then attempt the full DSSSB TGT / PGT papers as timed tests to check your speed under exam conditions.

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