Digital Logic & Number Systems Previous Year Questions

Explanation

3245 ÷ 16 = 202 remainder 13 (D); 202 ÷ 16 = 12 remainder 10 (A); 12 = C. Reading upward gives CAD.

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Replace each hex digit with 4 bits: 7 = 0111, A = 1010, 4 = 0100, giving 011110100100 = 11110100100.

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The program counter holds the address of the next instruction to be fetched and executed.

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X + X'Y = (X + X')(X + Y) = 1·(X + Y) = X + Y, by the distributive law.

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Going up the hierarchy, size grows and speed falls: registers, then cache, then main memory, then solid-state disk.

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An XOR gate with an inverting bubble at the output computes (A⊕B)', which is the Exclusive-NOR gate.

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In a JK flip-flop, J = 0 and K = 0 is the hold condition, so the output does not change at the clock edge.

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AC + ABC = AC(1 + B) = AC, so a single 2-input AND gate is enough.

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In Java, String is a class (a reference type), not a primitive type. boolean, byte and double are primitives.

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A 4-bit parallel (ripple-carry) adder uses one half adder for the least significant bit, which has no carry-in, and three full adders for the other three bits.

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By De Morgan's law, (A·B)' = A' + B'.

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A binary storage cell with input, output and Read/Write control lines is the basic building block of a memory. Each cell stores one bit, which is read or written as the control lines select.

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In a synchronous parallel-load shift register, all 8 bits enter their flip-flops at the same time. So a single clock pulse loads the whole byte.

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Answer as per the book's key (b): * is binary multiplication and unary dereference. Note that − is also both unary and binary.

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Decreasing access time means going from slowest to fastest: magnetic tape, magnetic disk, main memory, register. Option A wrongly puts cache before main memory.

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A 16-to-1 MUX has 16 data inputs + 4 select lines = 20 inputs. A PROM needs 2²⁰ words × 1 output bit = 1M × 1.

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24 = 0000 0000 0001 1000. Invert the bits (1111 1111 1110 0111) and add 1 to get 1111 1111 1110 1000, which is −24 in 2's complement.

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A*(B+C)/D is evaluated as (A*(B+C))/D. In prefix form this is / * A + B C D.

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(A+C)(AB'+AC) = AB' + AC by absorption. Multiplying by (A' + B' + C') gives AB' + AB'C = AB'.

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The NOR gates give (A+B)' and (C+D)', and the AND gate combines them, so the output is (A+B)' · (C+D)'.

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By the absorption law, a + a·b = a(1 + b) = a·1 = a.

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In immediate addressing the operand value itself is part of the instruction; in ADD R4, #3 the constant 3 (marked by #) is used directly, with no memory lookup.

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a'b + ab' is 1 only when a and b differ, which is exactly the definition of XOR (a ⊕ b).

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The 1s fill the rows cd = 01 and cd = 11 for every value of ab. In both rows d = 1, while c and a, b change, so the expression is F = d.

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Minterms 0, 4, 8 and 12 are exactly the cells where Y = 0 and Z = 0, whatever W and X are. These four cells form one group, so F = Y'Z'.

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Cache is a small, fast memory between the CPU and main memory. It gives near-register speed for frequently used data, while the large cheaper main memory provides the size.

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132A in hex = 0001 0011 0010 1010 in binary. Regrouping in 3s from the right gives 1 001 100 101 010 = 11452 in octal.

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4096 = 2¹², which in binary is 1 followed by twelve 0s. That needs 13 bits (12 bits can go only up to 4095).

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B ⊕ C = B ⊕ (A ⊕ B) = A ⊕ (B ⊕ B) = A ⊕ 0 = A.

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The first OR gate gives A + B', which is ANDed with C' to give (A + B')·C'. This result is ORed with D, so the output is (A + B')·C' + D.

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The program counter always holds the address of the next instruction to be fetched; it is incremented (or loaded with a branch target) after each fetch.

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When BG = 1 the CPU has given up the buses and the DMA controller is the bus master, so its RD and WR lines become outputs that control memory reads and writes.

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+28 in 16 bits is 0000000000011100. Inverting the bits gives 1111111111100011, and adding 1 gives 1111111111100100.

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By the consensus theorem, BC is redundant: BC = BC(A + A') = ABC + A'BC, which is absorbed by AB and A'C. So AB + A'C + BC = AB + A'C.

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NAND (and NOR) are universal gates because any Boolean function, including NOT, AND and OR, can be built using only NAND gates.

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In BCD each decimal digit is coded separately in 4 bits: 4 = 0100, 5 = 0101, 8 = 1000, 9 = 1001, giving 0100 0101 1000 1001.

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A decimal-to-BCD encoder has 10 inputs (one for each digit 0-9) and 4 outputs (the 4-bit BCD code).

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A demultiplexer takes one input and routes it to one of several outputs according to select lines. A multiplexer does the opposite.

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The 1-cells are A'B'C'D' and ABC'D' (CD=00), A'BC'D and AB'C'D (CD=01), and ABCD (CD=11). Adding these five minterms gives option (B).

Explanation

25 = (11001)₂. For 0.625: ×2 = 1.25 (1), 0.25×2 = 0.5 (0), 0.5×2 = 1.0 (1), giving .101. So 25.625 = (11001.101)₂.

Explanation

An AND gate gives a high output only when all inputs are high, half a byte (4 bits) is a nibble, and a D flip-flop's output follows its D input on the clock edge.

Explanation

27 = (11011)₂. The Gray code keeps the MSB and XORs adjacent bits: 1, 1⊕1=0, 0⊕1=1, 1⊕0=1, 1⊕1=0, giving 10110.

Explanation

Y = (A + BC)(B + AC') = AB + AC' + BC. AB is the consensus term of BC and AC', so Y = BC + AC'. Also (A + C)(B + C') = AB + AC' + BC, the same function, so both are correct.

Explanation

Q0 toggles on every clock and Q1 toggles whenever Q0 goes 0→1 (it is clocked by Q0). From 00: Q0→1 so Q1 toggles (11); then Q0→0 (10); then Q0→1 so Q1 toggles (01). This is a down counter.

Explanation

The Break All button pauses (breaks) execution of the running program so it can be debugged. It does not delete items.

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Breaking a program into modules makes it easier to use and maintain, and lets the modules be reused in other programs.

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A frame buffer with one bit per pixel is a bitmap, and one with multiple bits per pixel (for colour or grey levels) is a pixmap.

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Half duplex is two-way but only one direction at a time, not "multidirectional". Full duplex is bidirectional at the same time. So only II is true.

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The motivation comes from the pleasure of doing the activity itself, not from an outside reward, so it is intrinsic motivation.

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Both statements are correct: classical conditioning conditions elicited (respondent) behaviour, and operant conditioning conditions emitted behaviour. So neither is incorrect.